Part Number Hot Search : 
904BC THV314 KSC1395 GMV2100 M69000 JANSR2N MAX3362 BU2525AW
Product Description
Full Text Search
 

To Download PJCLAMP0502Q Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 PJCLAMP0502Q
DUAL ULTRA LOW CAPACITANCE ESD PROTECTOR ARRAY
This Dual Unidirectional ESD Protector Array family have been designed to protect sensitive equipment against ESD in high speed transmission buses, operating at 5V and demanding the lowest insertion loss. This array offers an integrated solution to protect up to 2 data lines in applications, where the board space is a premium, in a Quad Flat no-Lead package that only occupies an area of 1.8 sq mm. 6 5
PRELIMINARY
SPECIFICATION FEATURES
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Low Leakage Current, Maximum of 1A at rated voltage Maximum Capacitance of 1pF per device at 0Vdc 1MHz Peak Power Dissipation of 40W 8/20s Waveform Quad Flat No Lead package QFN (1.2x1.5 sq mm, Height: 0.75mm) Lead Free Package 100% Tin Plating, Matte finish
4
1
1
2
3
1
2
3
APPLICATIONS
USB2.0 and IEEE 1394 Firewire Ports RF Power Amplifier Protection RF/Antenna Circuits
6 5 4
QFN 1.2x1.5 sq mm
MAXIMUM RATINGS (Per Device)
Rating Peak Pulse Power (8/20s Waveform) Peak Pulse Current (8/20s Waveform) ESD Voltage (HBM Per MIL STD883C - Method 3015-6) Operating Temperature Range Storage Temperature Range Symbol P PP I PPM V ESD TJ Tstg Value 40 3 25 -55 to +150 -55 to +150 Units W A kV C C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25C
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Off State Junction Capacitance Symbol V WRM VBR IR Vc Cj I BR = 1mA VR = 5V I pp = 3A
0 Vdc Bias f = 1MHz between 4&2 or 6&2
Conditions
Min
Typical
Max 5
Units V V
6 1 12 1
A V pF
1/25/2006
Page
1
www.panjit.com
PJCLAMP0502Q
TYPICAL CHARACTERISTIC CURVES (Per Device)
Tj = 25C
Capacitance, pF
PRELIMINARY
Clamping Voltage vs 8/20s Ipp
Pulse Waveform 110 100 90 Percent of Ipp
4
Ipp, Amps
3
80 70 60 50 40 30 20 10 0 Rise time 10-90% - 8s
50% of Ipp @ 20s
2
1 8 8.5 9 9.5 10 10.5 11 11.5 12 Clamping Voltage, V
0
5
10
15 time, sec
20
25
30
Typical Capacitance vs. Bias Voltage @1MHz 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 Bias Voltage, Vdc 4 5
1/25/2006
Page 2
www.panjit.com
PJCLAMP0502Q
PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT
0.300.05 mm 1.50.05 mm
PRELIMINARY
25.0 23.0 12.0
0.60.05 mm
1.20.05 mm 0.200.05 mm
0.350.05 mm
0.5 mm
22.04 mm
0.750.025 mm
0.20.025 mm
16 mil
31 mil
49.0
24 mil
55 mil
19.7
39 mil
Suggested Pad Layout (in mils)
Alternate Pad Layout SOT523 (in mils)
1/25/2006
Page 3
www.panjit.com


▲Up To Search▲   

 
Price & Availability of PJCLAMP0502Q

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X